In each of the first and second GAA FETs, the semiconductor wires 25, which are channel layers, are disposed over the substrate 10. In some embodiments, the semiconductor wires 25 are disposed over a fin structure (not shown) protruding from the substrate 10. Each of the channel layers 25 is wrapped around by a gate dielectric layer 53 and a gate electrode layer 58. In some embodiments, the gate dielectric layer 53 includes an interfacial layer 52 and a high-k dielectric layer 54. The gate structure includes the gate dielectric layer 53, the gate electrode layer 58 and sidewall spacers 32. Although FIG. 1 shows four semiconductor wires 25, the number of the semiconductor wires 25 is not limited to four, and may be as small as one or more than four and may be up to fifteen (15).

In certain embodiments of the present disclosure, one or more work function adjustment layers 56 are interposed between the gate dielectric layer 53 and the gate electrode layer 58.

In each of the first and second GAA FETs, a source/drain epitaxial layer 40 is disposed over the substrate 10. The source/drain epitaxial layer 40 is in direct contact with the channel layer 25, and is separated by a dielectric layer 35 as inner spacers and the gate dielectric layer 53 from the gate electrode layer 58. The dielectric layer 35 is made of a low-k (low dielectric constant lower than the dielectric constant of SiO₂) material. The low-k material includes SiOC, SiOCN, organic material or porous material, or any other suitable material.