A chip packaging structure of the disclosure includes a heat dissipation substrate, a pre-molded chipset, an interconnection, and a second encapsulant. The pre-molded chipset is located on the heat dissipation substrate. The interconnection is located in the packaging structure and electrically connects the heat dissipation substrate and the pre-molded chipset. The second encapsulant covers part of the heat dissipation substrate, part or all of the interconnection, and part or all of the pre-molded chipset. The pre-molded chipset includes a thermally conductive substrate, at least two chips, a patterned circuit, and a first encapsulant. The at least two chips are located on the thermally conductive substrate and thermally coupled to the thermally conductive substrate. The patterned circuit is located in the pre-molded chipset. The at least two chips are electrically connected by the patterned circuit. The first encapsulant covers the at least two chips and part or all of the patterned circuit.