The exemplary embodiments of the disclosure will be fully described below with reference to the drawings, but the disclosure may also be implemented in various different forms and should not be construed as being limited to the embodiments described herein. In the drawings, for the purpose of clarity, the size and thickness of each region, location, and layer may not be drawn to actual scale. To facilitate understanding, the same elements in the following description will be described with the same reference numerals.

Unless clearly stated otherwise, any method described herein is in no way intended to be interpreted as requiring the steps to be performed in a specific order.

FIG. 1 is a schematic cross-sectional view of a chip packaging structure according to an embodiment of the disclosure. FIG. 2A to FIG. 2H are three-dimensional schematic views of a chip packaging structure in different stages of a manufacturing process according to an embodiment of the disclosure. FIG. 3A is a schematic cross-sectional view of an electrical connection mode of at least two chips of a chip packaging structure according to an embodiment of the disclosure.