Semiconductor package with solder standoff
地域：
TX
TX Dallas
摘要
A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.
說明書
This Disclosure relates to semiconductor packages including at least one semiconductor die that includes solder connection(s).
Some semiconductor die packages use metal clips instead of wires to form internal connections to terminals on the semiconductor die and to provide external terminals, sometimes being called clip packages. For example some power packages include a single vertical field effect transistor (FET) die, while other power packages include multichip module (MCM) packages with laterally placed high side vertical FET die and low side vertical FET die FET die, while other MCM packages include vertically stacked FET die including a high side vertical FET die and a low side vertical FET die that conventionally include a plurality of clips. Clip packages generally have better electrical and thermal performance as compared to semiconductor die packages that utilize bond wire-based electrical connections.
Typically, conventional clip packages are designed into a customer's printed circuit boards (PCBs) because the circuit boards have unique footprints and pin assignments. When producing clip packages, one known problem is the forming of an uneven bond line thickness (BLT) of solder between the clip and the metal connections on the vertical die. When there is an uneven BLT of solder between a vertical die and a clip, the resulting semiconductor package may have clip and/or die tilting leading to thin solder regions, which may lead to reliability problems such as during heat cycling, and the power package may also exhibit degraded electrical performance such as due to solder cracking, which can lead to higher resistance or can cause shorts.
權(quán)利要求
The invention claimed is:1. A semiconductor package, comprising:a leadframe including a die pad and a plurality of lead terminals; a vertical semiconductor device attached on a first side by a die attach material to the die pad, a first clip on the first vertical device that is solder connected to a terminal of the vertical semiconductor device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the plurality of lead terminals; wherein the first solder bonded interface includes a first non-metallic protruding surface standoff therein that extends from a surface on the second side of the vertical device to physically contact the first clip. 2. The semiconductor package of claim 1 , wherein the vertical semiconductor device comprises a vertical power field effect transistor (FET). 3. The semiconductor package of claim 1 , wherein the vertical semiconductor device comprises a first vertical device and a second vertical device. 4. The semiconductor package of claim 3 , wherein the first vertical semiconductor device and the second vertical semiconductor device are vertically stacked. 5. The semiconductor package of claim 3 , wherein the first vertical semiconductor device and the second vertical semiconductor device are laterally positioned with respect to one another. 6. The semiconductor package of claim 1 , wherein the first protruding surface standoff comprises a ring having a protruding height of 10 to 30 μm. 7. The semiconductor package of claim 1 , wherein the vertical semiconductor device comprises a first vertical power field effect transistor (FET) and a second vertical power FET. 8. A multichip module (MCM) power package, comprising:a leadframe including a die pad and a plurality of lead terminals; stacked vertical power field effect transistors (FETs), comprising:a first vertical FET die attached to the die pad; a first clip on the first vertical FET die that is solder connected to a terminal of the first vertical FET die providing a first solder bonded interface, wherein the first clip is connected to at least a first of the plurality of lead terminals; a second vertical FET die over the first clip having a terminal solder connected to the first clip providing a second solder bonded interface; a second clip solder connected to another terminal of the second vertical FET die to provide a third solder bonded interface, where the second clip is connected to at least a second of the plurality of lead terminals, and wherein at least one of the first, the second, and the third solder bonded interfaces include a non-metallic protruding surface standoff therein that extends from a surface of the first or the second vertical FET die to contact the first clip, or the second clip. 9. The MCM power package of claim 8 , wherein the protruding surface standoff comprises a ring having a protruding height of 10 to 30 μm. 10. The MCM power package of claim 8 , wherein the protruding surface standoff is circular in shape and has a center diameter of 0.1 to 0.3 mm, and has a protruding height of 10 to 30 μm. 11. A semiconductor package, comprising:a leadframe including a die pad and a plurality of lead terminals; a vertical semiconductor device attached on a first side by a die attach material to the die pad, a first clip on the first vertical device that is solder connected to a terminal of the vertical semiconductor device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the plurality of lead terminals; wherein the first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the vertical device to physically contact the first clip; and wherein the die attach material comprises solder providing a second solder bonded interface, and wherein the second solder bonded interface includes a second protruding surface standoff therein that extends from the first side of the first vertical semiconductor device to physically contact the die pad. 12. A semiconductor package, comprising:a leadframe including a die pad and a plurality of lead terminals; a vertical semiconductor device attached on a first side by a die attach material to the die pad, a first clip on the first vertical device that is solder connected to a terminal of the vertical semiconductor device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the plurality of lead terminals; wherein the first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the vertical device to physically contact the first clip; and wherein the first protruding surface standoff comprises a second layer of passivation on the first vertical semiconductor device that has a blanket first layer of passivation provided across an area of the second side except for bond pad areas under the second layer of passivation. 13. A multichip module (MCM) power package, comprising:a leadframe including a die pad and a plurality of lead terminals; stacked vertical power field effect transistors (FETs), comprising:a first vertical FET die attached to the die pad; a first clip on the first vertical FET die that is solder connected to a terminal of the first vertical FET die providing a first solder bonded interface, wherein the first clip is connected to at least a first of the plurality of lead terminals; a second vertical FET die over the first clip having a terminal solder connected to the first clip providing a second solder bonded interface; a second clip solder connected to another terminal of the second vertical FET die to provide a third solder bonded interface, where the second clip is connected to at least a second of the plurality of lead terminals; wherein at least one of the first, the second, and the third solder bonded interfaces include a protruding surface standoff therein that extends from a surface of the first or the second vertical FET die to contact the first clip, or the second clip; and a controller integrated circuit including a driver on the die pad, and bond wires coupling an output of the driver to a gate of the first vertical FET die and to a gate of the second vertical FET die. 14. A multichip module (MCM) power package, comprising:a leadframe including a die pad and a plurality of lead terminals; stacked vertical power field effect transistors (FETs), comprising:a first vertical FET die attached to the die pad; a first clip on the first vertical FET die that is solder connected to a terminal of the first vertical FET die providing a first solder bonded interface, wherein the first clip is connected to at least a first of the plurality of lead terminals; a second vertical FET die over the first clip having a terminal solder connected to the first clip providing a second solder bonded interface; a second clip solder connected to another terminal of the second vertical FET die to provide a third solder bonded interface, where the second clip is connected to at least a second of the plurality of lead terminals; wherein at least one of the first, the second, and the third solder bonded interfaces include a protruding surface standoff therein that extends from a surface of the first or the second vertical FET die to contact the first clip, or the second clip; and wherein first, the second, and the third solder bonded interfaces all include the protruding surface standoff. 15. A multichip module (MCM) power package, comprising:a leadframe including a die pad and a plurality of lead terminals; stacked vertical power field effect transistors (FETs), comprising:a first vertical FET die attached to the die pad; a first clip on the first vertical FET die that is solder connected to a terminal of the first vertical FET die providing a first solder bonded interface, wherein the first clip is connected to at least a first of the plurality of lead terminals; a second vertical FET die over the first clip having a terminal solder connected to the first clip providing a second solder bonded interface; a second clip solder connected to another terminal of the second vertical FET die to provide a third solder bonded interface, where the second clip is connected to at least a second of the plurality of lead terminals, and wherein at least one of the first, the second, and the third solder bonded interfaces include a protruding surface standoff comprising a solder mask, a dry film, a polyimide, silicon nitride, or an epoxy therein that extends from a surface of the first or the second vertical FET die to contact the first clip, or the second clip. 16. A multichip module (MCM) power package, comprising:a leadframe including a die pad and a plurality of lead terminals; stacked vertical power field effect transistors (FETs), comprising:a first vertical FET die attached to the die pad; a first clip on the first vertical FET die that is solder connected to a terminal of the first vertical FET die providing a first solder bonded interface, wherein the first clip is connected to at least a first of the plurality of lead terminals; a second vertical FET die over the first clip having a terminal solder connected to the first clip providing a second solder bonded interface; a second clip solder connected to another terminal of the second vertical FET die to provide a third solder bonded interface, where the second clip is connected to at least a second of the plurality of lead terminals; wherein at least one of the first, the second, and the third solder bonded interfaces include a protruding surface standoff therein that extends from a surface of the first or the second vertical FET die to contact the first clip, or the second clip; and wherein the protruding surface standoff comprises a second layer of passivation on at least one of the first and second vertical FET die that has a first layer of passivation under the second layer of passivation. 17. A method of semiconductor device package assembly, comprising:providing a leadframe including a die pad and a plurality of lead terminals, a vertical semiconductor device including a first side and a second side including one of the first side and the second side having a non-metallic protruding surface standoff; attaching the first side of the first vertical semiconductor device using a die attach material to the die pad; solder connecting a first clip to a terminal on the second side of the first vertical semiconductor device to provide a first solder bonded interface, wherein the first clip is connected to at least one of the plurality of lead terminals. 18. The method of claim 17 , wherein the first vertical semiconductor device comprises a first vertical power field effect transistor (FET). 19. The method of claim 18 , further comprising assembling a second vertical power FET device on the first clip. 20. The method of claim 19 , further comprising attaching a controller integrated circuit including a driver on the die pad, and positioning bond wires coupling an output of the driver to a gate of the first vertical FET and to a gate of the second vertical FET. 21. The method of claim 17 , further comprising assembling a second vertical device laterally positioned with respect to the first vertical device. 22. The method of claim 17 , wherein the protruding surface standoff comprises a ring having a protruding height of 10 to 30 μm. 23. A method of semiconductor device package assembly, comprising:providing a leadframe including a die pad and a plurality of lead terminals, a vertical semiconductor device including a first side and a second side including one of the first side and the second side having a protruding surface standoff; attaching the first side of the first vertical semiconductor device using a die attach material to the die pad; solder connecting a first clip to a terminal on the second side of the first vertical semiconductor device to provide a first solder bonded interface, wherein the first clip is connected to at least one of the plurality of lead terminals, wherein the die attach material comprises solder providing a second solder bonded interface, and wherein the second solder bonded interface includes another protruding surface standoff therein that extends from the first side of the first vertical semiconductor device to physically contact the die pad. 24. A method of semiconductor device package assembly, comprising:providing a leadframe including a die pad and a plurality of lead terminals, a vertical semiconductor device including a first side and a second side including one of the first side and the second side having a protruding surface standoff; attaching the first side of the first vertical semiconductor device using a die attach material to the die pad; and solder connecting a first clip to a terminal on the second side of the first vertical semiconductor device to provide a first solder bonded interface, wherein the first clip is connected to at least one of the plurality of lead terminals, wherein the protruding surface standoff comprises a second layer of passivation on the first vertical semiconductor device that has a blanket first layer of passivation provided across an area of the second side except for bond pad areas under the second layer of passivation.
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