This Disclosure relates to semiconductor packages including at least one semiconductor die that includes solder connection(s).

Some semiconductor die packages use metal clips instead of wires to form internal connections to terminals on the semiconductor die and to provide external terminals, sometimes being called clip packages. For example some power packages include a single vertical field effect transistor (FET) die, while other power packages include multichip module (MCM) packages with laterally placed high side vertical FET die and low side vertical FET die FET die, while other MCM packages include vertically stacked FET die including a high side vertical FET die and a low side vertical FET die that conventionally include a plurality of clips. Clip packages generally have better electrical and thermal performance as compared to semiconductor die packages that utilize bond wire-based electrical connections.

Typically, conventional clip packages are designed into a customer's printed circuit boards (PCBs) because the circuit boards have unique footprints and pin assignments. When producing clip packages, one known problem is the forming of an uneven bond line thickness (BLT) of solder between the clip and the metal connections on the vertical die. When there is an uneven BLT of solder between a vertical die and a clip, the resulting semiconductor package may have clip and/or die tilting leading to thin solder regions, which may lead to reliability problems such as during heat cycling, and the power package may also exhibit degraded electrical performance such as due to solder cracking, which can lead to higher resistance or can cause shorts.