FIG. 5A is a top perspective view without the mold compound shown of an 8-pin semiconductor clip package 500 having only a single die 510 (e.g., comprising silicon) including both a first vertical FET 130a and a second vertical FET 140a positioned lateral to one another, where the die 510 is flipchip attached to the leadframe 110. The gate G and source S terminals for each of the vertical FETs 130a, 140a are also identified in FIG. 5A for explanation purposes even though they would not be visible because they would be facing downward due to the flipchip arrangement. The first vertical FET 130a and the second vertical FET 140a have their back side which is a common drain facing up coupled by a clip shown as 507 (see the clip 507 in the cross section view in FIG. 5B described below) which is a common drain clip, that is shown coupled to lead terminals 2 and 3 of the leadframe 110. There are disclosed protruding surface standoffs 152, 151 on both the die's 510 top side and back side, with the protruding surface standoffs 152 only being shown in FIG. 5A. (But see the protruding surface standoffs 151 and 152 shown in FIG. 5B and FIG. 5C described below).