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Semiconductor package with solder standoff

專利號(hào)
US11177197B2
公開日期
2021-11-16
申請(qǐng)人
Texas Instruments Incorporated(US TX Dallas)
發(fā)明人
Jonathan Almeria Noquil; Satyendra Singh Chauhan; Lance Cole Wright; Osvaldo Jorge Lopez
IPC分類
H01L23/495; H01L23/00; H01L25/07; H01L25/00; H01L25/16; H01L21/56; H01L23/31
技術(shù)領(lǐng)域
die,fet,solder,clip,standoff,standoffs,vertical,protruding,package,leadframe
地域: TX TX Dallas

摘要

A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.

說明書

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This Summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described below in the Detailed Description including the drawings provided. This Summary is not intended to limit the claimed subject matter's scope.

Disclosed aspects recognize semiconductor packages having vertical semiconductor die(s) (vertical die) with solder connections that utilize at least one clip may as assembled have an uncontrolled BLT of solder resulting in clip and die tilting. The cause of these problems is recognized to be because during a solder reflow process the solder reflow tends to move the clip and the vertical die in z (height) direction causing tilt, and as a result non-uniformity in the BLT of the solder.

權(quán)利要求

1
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