FIG. 4A is an exploded view of a disclosed stacked die MCM power package having an optional controller IC, shown wire bonded to the gate of the LS vertical FET, with bond wires from the controller IC to the gate of the HS FET not shown in FIG. 4A (due to the exploded view), with the vertical FET die each having disclosed standoffs shown as posts. Protruding standoffs shown as posts are shown on the top side of the HS FET and protruding standoffs shown as posts are shown on the top side of the LS FET.

FIG. 4B shows a stacked die MCM power package having the optional controller IC shown in FIG. 4A therein, no longer shown exploded, where bond pads are now shown on the controller IC, on the LS FET, and on the HS FET. Although not revealed, there are generally disclosed protruding standoffs on both sides of the respective HS FET and the LS FET.

FIG. 5A is a top perspective view without mold compound shown of a semiconductor clip flipchip package including monolithic die having both a first vertical FET and a second vertical FET lateral to the first vertical FET, including disclosed standoffs on both its top side and back side, where the die is flipchip attached to clips that are coupled to terminals of the leadframe, and where the vertical FETs have their top side which is a common drain coupled by a single clip to 2 lead terminals of the leadframe. FIGS. 5B and 5C are cross-sectional views of the semiconductor clip flip to package shown in FIG. 5A along the cut lines 5B-5B and 5C-5C respectively, now showing the mold compound.