FIG. 1A is a top perspective view of an example semiconductor package 100 without the mold compound shown including a vertical semiconductor die 140 connected to a clip 107 by a solder bonded interface connection 192 that includes a protruding surface solder standoff (solder standoff) on both sides of the vertical semiconductor die 140 shown as 152 (on the top side) and 151 (on the back side). The clip 107 can comprise copper or a copper alloy. In FIG. 2A to FIG. 6 described below, the vertical semiconductor die 140 is described as being a low side FET die (LS FET) 140. The solder standoffs can be seen to extend the full distance from the top side of the vertical semiconductor die 140 to physically contact the clip 107. The vertical semiconductor die 140 comprises a three-terminal device, such as a bipolar device, a FET device such as a MOSFET device, or an insulated-gate bipolar transistor (IGBT) device. The vertical semiconductor die can comprise a silicon substrate, a III-V substrate such as gallium nitride, or a II-VI substrate.