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Alignment through topography on intermediate component for memory device patterning

專利號(hào)
US11177437B2
公開日期
2021-11-16
申請(qǐng)人
International Business Machines Corporation（US NY Armonk）
發(fā)明人
Hao Tang; Michael Rizzolo; Injo Ok; Theodorus E. Standaert
IPC分類
H01L45/00; H01L23/544; H01L27/24
技術(shù)領(lǐng)域
alignment,layer,dielectric,electrode,metal,assisting,mark,depositing,in,or
地域： NY NY Armonk

摘要

An intermediate semiconductor device structure includes a first area including a memory stack area and a second area including an alignment mark area. The intermediate structure includes a metal interconnect arranged on a substrate in the first area and a first electrode layer arranged on the metal interconnect in the first area, and in the second area. The intermediate structure includes an alignment assisting marker arranged in the second area. The intermediate structure includes a dielectric layer and a second electrode layer arranged on the alignment assisting marker in the second area and on the metal interconnect in the first area. The intermediate structure includes a hard mask layer arranged on the second electrode area. The hard mask layer provides a raised area of topography over the alignment assisting marker. The intermediate structure includes a resist arranged on the hard mask layer in the first area.

說明書

DOMESTIC PRIORITY

This application is a divisional of U.S. patent application Ser. No. 16/019,798, filed Jun. 27, 2018, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to alignment through topography on an intermediate component for memory device patterning.

Integrated circuit chips are fabricated one level at a time. The levels include, for example, diffusions, gates, metal lines, insulation, isolation, and contacts. The structures on these levels must be precisely positioned so that the finished chip has properly positioned structures. The step of positioning a level with respect to a previously formed level is called alignment.

Alignment of patterned materials involves manual or automatic selection of alignment targets. The alignment targets typically include “alignment marks” that a recognition system uses to learn a position of the part or material subject to examination. A user or computer then provides a region of interest (ROI) by moving to the selected location, while the software records this coordinate. Alternatively, a coordinate relative to some known reference point (e.g., center of the part) is indicated by the software. Once the setup is completed (i.e., after the alignment marks are recorded), the optical system aligns and moves to a ROI on the part for measurement or inspection.

SUMMARY

權(quán)利要求

1
What is claimed is:1. A semiconductor device comprising:a first area comprising a memory stack area;a second area comprising an alignment mark area;a metal interconnect arranged on a substrate in the first area;a first electrode layer that is a continuous single layer that extends from the first area to the second area and arranged on the metal interconnect in the first area;an alignment assisting marker arranged in the second area, the alignment assisting marker being a raised portion of a film arranged directly on the first electrode layer and on the memory stack area of the first area;a dielectric layer and a second electrode layer arranged on the alignment assisting marker in the second area, the dielectric layer arranged directly on the first electrode layer in the first area and extends as a continuous single layer to the second area;a hard mask layer arranged on the second electrode area, the hard mask layer providing a raised area of topography over the alignment assisting marker; anda resist arranged on the hard mask layer in the first area.2. The semiconductor device of claim 1, wherein the first electrode layer comprises a metal.3. The semiconductor device of claim 2, wherein the second electrode layer comprises a metal.4. The semiconductor device of claim 1, wherein the first electrode layer comprises platinum, copper, silver, gold, ruthenium, iridium, nickel, titanium, titanium nitride, tantalum, tantalum nitride, zirconium nitride, or a combination thereof.5. The semiconductor device of claim 1, wherein the second electrode layer comprises platinum, copper, silver, gold, ruthenium, iridium, nickel, titanium, titanium nitride, tantalum, tantalum nitride, zirconium nitride, or a combination thereof.6. The semiconductor device of claim 1, wherein the film of the alignment assisting marker is a non-metallic material.7. The semiconductor device of claim 1, wherein the film of the alignment assisting marker has an etch selectivity against the first electrode layer.8. The semiconductor device of claim 1, wherein the film of the alignment assisting marker has a thickness of about 5 to about 200 nanometers (nm).9. The semiconductor device of claim 1, wherein the film of the alignment assisting marker is silicon dioxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide (SiCOH), silicon carbonitride, spin-on-glass, aluminum oxide, polymers such as parylene, crosslinked polyphenylenes, poly(arylene ethers), or a combination thereof.10. The semiconductor device of claim 1, wherein the resist comprises a planarization layer, an anti-reflective coating, and a resist layer.
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