The dielectric layer 101 includes, but is not limited to, a low-k dielectric oxide, for example, silicon dioxide, spin-on-glass, a flowable oxide, a high-density plasma oxide, or any combination thereof. The dielectric layer 101 can be formed by performing deposition process, including, but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD, atomic layer deposition (ALD), evaporation, chemical solution deposition, or like processes.

To form the metal interconnect 102 (also referred to as a conductive interconnect), a trench is etched in the dielectric layer 101. The trench is filled with one or more liner layers, followed by one or more metals. Non-limiting examples of materials for the metal forming the metal interconnect 102 include copper, copper alloys, aluminum, aluminum alloys, tungsten, tungsten silicide, cobalt, molybdenum, titanium nitride, tantalum, tantalum nitride, or any combination thereof. A planarization process, e.g., CMP, is performed to remove excess metal(s) from the surface of the dielectric layer 101.