FIG. 2 depicts a cross-sectional side view of the semiconductor device 100 subsequent to, optionally, forming a metal connector 208 on the metal interconnect 102. The metal connector 208 can be included to prevent metal, e.g., copper, diffusion from the metal interconnect 102 into memory stack. A dielectric layer 204 is deposited on the metal interconnect 102. Lithography and etching are used to form a trench in the dielectric layer 204 over the metal interconnect 102, and one or more metals are deposited in the trench to form the metal connector 208. Non-limiting examples of the dielectric layer 204 include silicon dioxide, silicon nitride, silicon oxynitride, silicon carbonitride, spin-on-glass, or a combination thereof. Non-limiting examples of metals for the metal connector 208 include niobium, tantalum, tantalum nitride, titanium nitride, molybdenum, tungsten, cobalt, or a combination thereof. A planarization process, e.g., CMP, is then performed to polish the surface of the dielectric layer 204.