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Alignment through topography on intermediate component for memory device patterning

專利號(hào)
US11177437B2
公開日期
2021-11-16
申請(qǐng)人
International Business Machines Corporation(US NY Armonk)
發(fā)明人
Hao Tang; Michael Rizzolo; Injo Ok; Theodorus E. Standaert
IPC分類
H01L45/00; H01L23/544; H01L27/24
技術(shù)領(lǐng)域
alignment,layer,dielectric,electrode,metal,assisting,mark,depositing,in,or
地域: NY NY Armonk

摘要

An intermediate semiconductor device structure includes a first area including a memory stack area and a second area including an alignment mark area. The intermediate structure includes a metal interconnect arranged on a substrate in the first area and a first electrode layer arranged on the metal interconnect in the first area, and in the second area. The intermediate structure includes an alignment assisting marker arranged in the second area. The intermediate structure includes a dielectric layer and a second electrode layer arranged on the alignment assisting marker in the second area and on the metal interconnect in the first area. The intermediate structure includes a hard mask layer arranged on the second electrode area. The hard mask layer provides a raised area of topography over the alignment assisting marker. The intermediate structure includes a resist arranged on the hard mask layer in the first area.

說(shuō)明書

The alignment marks/alignment assisting components described in this invention are not limited to scanner alignment marks. By placing multiple marks/components in different shapes and meeting the specifications of different purposes/tools, the alignment mark/alignment assisting component can serve as overlay marks for overlay metrology, alignment marks for CDSEM (Critical Dimension Scanning Electron Microscope), alignment marks for defect inspection tools, etc.

FIG. 9 depicts a cross-sectional side view of the semiconductor device 100 subsequent to depositing a resist stack 930 on the hard mask layer 820. The resist stack 930 can include, for example, a planarization layer 920 (e.g., an organic planarization layer (OPL) or other spin-on polymeric coating), an anti-reflective layer 922, and a resist 924 (e.g., a photoresist); although, the resist stack 930 is not limited to these layers and materials. The resist 924 can be patterned by lithographic exposure. The pattern formed by the resist 924 will be transferred through the layers beneath to form the RRAM memory stack over the metal interconnect 102 in the first area 510. The resist 924 is aligned to the alignment mark 505 through the raised topography created at the hard mask layer 820, as the layers of the resist stack 930 (planarization layer 920 and anti-reflective layer 922) are transparent.

權(quán)利要求

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