Another non-limiting example of the method includes forming a metal interconnect in a first area of the semiconductor device. The method includes depositing a first electrode layer on the metal interconnect. The method further includes depositing and patterning a film on the first electrode layer to form an alignment assisting marker is a second area of the semiconductor device proximate to the first area. The method includes depositing a dielectric layer and a second electrode layer on the alignment assisting marker in the second area and on the metal interconnect in the first area. The method includes depositing a metal connector layer on the second electrode layer. The method further includes depositing a hard mask layer on the metal connector layer to create a raised area of topography over the alignment assisting marker. The method includes depositing and patterning a resist on the hard mask layer, using the raised area of topography created by the hard mask layer over the alignment assisting marker to align the resist over the metal interconnect in the first area of the semiconductor device. The method further includes etching to form a memory stack over the metal interconnect by transferring the pattern of the resist into the first electrode layer, the dielectric layer, and the second electrode layer in the first area of the semiconductor device.