Embodiments of the invention are directed to an intermediate semiconductor device structure. A non-limiting example of the intermediate semiconductor device structure includes a first area including a memory stack area and a second area including an alignment mark area. The intermediate semiconductor device structure includes a metal interconnect arranged on a substrate in the first area and a first electrode layer arranged on the metal interconnect in the first area, and in the second area. The intermediate semiconductor device structure includes an alignment assisting marker arranged in the second area. The intermediate semiconductor device structure includes a dielectric layer and a second electrode layer arranged on the alignment assisting marker in the second area and on the metal interconnect in the first area. The intermediate semiconductor device structure includes a hard mask layer arranged on the second electrode area. The hard mask layer provides a raised area of topography over the alignment assisting marker. The intermediate semiconductor device structure includes a resist arranged on the hard mask layer in the first area.

Additional technical features and benefits are realized through the techniques of the present invention. Embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, refer to the detailed description and to the drawings.