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Alignment through topography on intermediate component for memory device patterning

專(zhuān)利號(hào)
US11177437B2
公開(kāi)日期
2021-11-16
申請(qǐng)人
International Business Machines Corporation(US NY Armonk)
發(fā)明人
Hao Tang; Michael Rizzolo; Injo Ok; Theodorus E. Standaert
IPC分類(lèi)
H01L45/00; H01L23/544; H01L27/24
技術(shù)領(lǐng)域
alignment,layer,dielectric,electrode,metal,assisting,mark,depositing,in,or
地域: NY NY Armonk

摘要

An intermediate semiconductor device structure includes a first area including a memory stack area and a second area including an alignment mark area. The intermediate structure includes a metal interconnect arranged on a substrate in the first area and a first electrode layer arranged on the metal interconnect in the first area, and in the second area. The intermediate structure includes an alignment assisting marker arranged in the second area. The intermediate structure includes a dielectric layer and a second electrode layer arranged on the alignment assisting marker in the second area and on the metal interconnect in the first area. The intermediate structure includes a hard mask layer arranged on the second electrode area. The hard mask layer provides a raised area of topography over the alignment assisting marker. The intermediate structure includes a resist arranged on the hard mask layer in the first area.

說(shuō)明書(shū)

The specifics of the exclusive rights described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIGS. 1-12 illustrate a process flow for fabricating a semiconductor device according to embodiments of the invention, in which:

FIG. 1 depicts cross-sectional side view of the semiconductor device including a metal interconnect arranged in a dielectric layer;

FIG. 2 depicts a cross-sectional side view of the semiconductor device subsequent to forming a metal connector on the metal interconnect;

FIG. 3 depicts a cross-sectional side view of the semiconductor device subsequent to depositing a first electrode (bottom electrode) on the metal connector;

FIG. 4 depicts a cross-sectional side view of the semiconductor device subsequent to depositing a film on the bottom electrode;

FIG. 5 depicts a cross-sectional side view of the semiconductor device subsequent to etching the film to form an alignment assisting marker;

FIG. 6 depicts a cross-sectional side view of the semiconductor device subsequent to depositing a dielectric layer on the bottom electrode as well as on the alignment assisting marker;

權(quán)利要求

1
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