FIG. 7 depicts a cross-sectional side view of the semiconductor device subsequent to depositing a second electrode (top electrode) on the dielectric layer;

FIG. 8 depicts a cross-sectional side view of the semiconductor device subsequent to depositing a metal connector layer and a hard mask layer on the top electrode;

FIG. 9 depicts a cross-sectional side view of the semiconductor device subsequent to depositing a resist stack on the hard mask layer;

FIG. 10 depicts a cross-sectional side view of the semiconductor device subsequent to etching to form a memory stack;

FIG. 11 depicts a cross-sectional side view of the semiconductor device subsequent to depositing an interlayer dielectric on the memory stack; and

FIG. 12 depicts a cross-sectional side view of the semiconductor device subsequent to forming a metal via to connect the memory device to the metal layer above.

The diagrams depicted herein are illustrative. There can be many variations to the diagram or the operations described therein without departing from the spirit of the invention. For instance, the actions can be performed in a differing order or actions can be added, deleted or modified. Also, the term “coupled” and variations thereof describes having a communications path between two elements and does not imply a direct connection between the elements with no intervening elements/connections between them. All of these variations are considered a part of the specification.