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Alignment through topography on intermediate component for memory device patterning

專利號
US11177437B2
公開日期
2021-11-16
申請人
International Business Machines Corporation(US NY Armonk)
發(fā)明人
Hao Tang; Michael Rizzolo; Injo Ok; Theodorus E. Standaert
IPC分類
H01L45/00; H01L23/544; H01L27/24
技術(shù)領(lǐng)域
alignment,layer,dielectric,electrode,metal,assisting,mark,depositing,in,or
地域: NY NY Armonk

摘要

An intermediate semiconductor device structure includes a first area including a memory stack area and a second area including an alignment mark area. The intermediate structure includes a metal interconnect arranged on a substrate in the first area and a first electrode layer arranged on the metal interconnect in the first area, and in the second area. The intermediate structure includes an alignment assisting marker arranged in the second area. The intermediate structure includes a dielectric layer and a second electrode layer arranged on the alignment assisting marker in the second area and on the metal interconnect in the first area. The intermediate structure includes a hard mask layer arranged on the second electrode area. The hard mask layer provides a raised area of topography over the alignment assisting marker. The intermediate structure includes a resist arranged on the hard mask layer in the first area.

說明書

In the accompanying figures and following detailed description of the described embodiments of the invention, the various elements illustrated in the figures are provided with two or three digit reference numbers. With minor exceptions, the leftmost digit(s) of each reference number correspond to the figure in which its element is first illustrated.

DETAILED DESCRIPTION

For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.

Turning now to an overview of technologies that are more specifically relevant to aspects of the invention, photolithography tools have alignment systems for aligning a level to be printed with a level already present on the wafer. The alignment system first determines the location of an alignment target on the wafer that was printed during a previous photolithographic process step. Once the location of the alignment target is established, the system adjusts the location of the wafer so the present level is printed at the proper location with respect to that previous level target. The previous level target can be the first level printed, the last level so far printed, or any level in between.

權(quán)利要求

1
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