The controller 55 may receive a vertical synchronization signal, a horizontal synchronization signal, and a clock signal and may generate a control signal for controlling operations of the first and second scan driving circuits 20 and 22. The generated control signal may be transmitted to the first and second scan driving circuits 20 and 22 through the terminal 44 connected to the FPCB and the connection wirings 21 and 31. Scan signals of the first and second scan driving circuits 20 and 22 may be applied to each pixel P through the scan line SL. The controller 55 may supply driving power ELVDD and common power ELVSS to the driving power supply line 60 and the common power supply line 70 through the terminals 42 and 45 connected to the FPCB and the connection wirings 61 and 71. The driving power ELVDD may be supplied to each pixel P through the driving voltage line PL. The common power ELVSS may be supplied to a common electrode of the pixel P.

A data driving circuit 50 may be located on the FPCB. The data driving circuit 50 may apply a data signal to each pixel P. The data signal of the data driving circuit 50 may be applied to each pixel P through the connection wiring 51 connected to the terminal 41 and the data line DL connected to the connection wiring 51. As shown in FIG. 1, the data driving circuit 50 may be located on the FPCB. In some implementations, the data driving circuit 50 may be located in the peripheral area PA of the lower substrate 100.