FIG. 9a provides a schematic diagram of a Ag NW enabled vertical polymer light emitting transistor with an ITO electrode on silicon wafer in accordance with embodiments of the invention;
FIG. 9b provides an SEM of a Ag NW network on a Si wafer (left) and an image of the printed MEH-PPV polymer (right) of the vertical polymer light emitting transistor of FIG. 9a in accordance with embodiments of the invention;
FIG. 10a provides a schematic diagram of a Ag NW enabled vertical polymer light emitting transistor with a Ag NW/PET electrode on silicon wafer in accordance with embodiments of the invention;
FIG. 10b provides an SEM of a Ag NW/PET electrode of FIG. 10a in accordance with embodiments of the invention;
FIG. 11 provides a schematic diagram of a singly-gated Ag NW enabled vertical polymer light emitting transistor with flexible electrodes, and a process diagram for its manufacture in accordance with embodiments of the invention;
FIG. 12 provides a schematic diagram of a doubly-gated Ag NW enabled vertical polymer light emitting transistor with flexible electrodes in accordance with embodiments of the invention; and
FIG. 13 provides a schematic diagram of a VLET display on ITO in accordance with embodiments of the invention.
DETAILED DESCRIPTION OF THE INVENTION
