In still yet other embodiments, the at least one conductive porous electrode is formed from a plurality of nanowires formed into one of the group of a random or patterned network of a plurality of metal or graphene nanowires, a nanowire metal mesh, a nanowire grid, and a nanowire network encased within an elastomeric material. In some such embodiments the plurality of nanowires are formed from a plurality of metal nanowires selected from Ag, Au and Cu having an aspect ratio of at least 1000. In other such embodiments the plurality of metal nanowires have a diameter less than about 200 nm and a length greater than about 1 micron, and having a surface coverage less than 10%, a sheet resistance less than 100Ω/sq and a transmission greater than 75%.

In still yet other embodiments, the dielectric material is selected from the group of an oxides selected from SiO₂, Al₂O₃, HfO₂, ZrO₂; a nitride; Si₃N₄; an inorganic salts selected from LiF, CsF, BaTiO₃, and SrTiO₃; a dielectric polymer selected from PMMA, Teflon, CYTOP, and Nafion; and an ionic gel formed from the combination of a dielectric polymer and an ionic liquid.

In still yet other embodiments, the vertical light emitting transistors may include at least one additional light emitting enhancement layer selected from the group consisting of electron injection dipole layers, transportation dipole layers, conjugate polyelectrolyte layers, and hole injection layers.

In still yet other embodiments the substrate is selected from the group consisting of flexible plastics, Si wafer, glass, sapphire, and ITO.

Other embodiments are directed to methods of forming vertical light emitting transistors, including: