FIG. 13 is a schematic cross-sectional view illustrating a semiconductor package according to another exemplary embodiment used in the antenna module.
Referring to FIG. 13, in a semiconductor package 200B according to another exemplary embodiment, a frame 210 may include a first insulating layer 211a, a first wiring layer 212a embedded in an upper side of the first insulating layer 211a so that an upper surface thereof is exposed, a second wiring layer 212b disposed on a lower surface of the first insulating layer 211a, a second insulating layer 211b disposed on the lower surface of the first insulating layer 211a and covering the second wiring layer 212b, and a third wiring layer 212c disposed on a lower surface of the second insulating layer 211b. Since the frame 210 may include a large number of wiring layers 212a, 212b, and 212c, a connection structure 240 may further be simplified. Therefore, a decrease in a yield depending on a defect occurring in a process of forming the connection structure 240 may be suppressed. The first and second wiring layers 212a and 212b and the second and third wiring layers 212b and 212c may be electrically connected to each other through first and second connection vias 213a and 213b penetrating through the first and second insulating layers 211a and 211b, respectively.
