Referring to FIG. 14, in a semiconductor package 200C, a frame 210 may include a first insulating layer 211a, a first wiring layer 212a and a second wiring layer 212b disposed on upper and lower surfaces of the first insulating layer 211a, respectively, a second insulating layer 211b disposed on the first insulating layer 211a and covering the first wiring layer 212a, a third wiring layer 212c disposed on an upper surface of the second insulating layer 211b, a third insulating layer 211c disposed on the lower surface of the first insulating layer 211a and covering the second wiring layer 212b, and a fourth wiring layer 212d disposed on a lower surface of the third insulating layer 211c. Since the frame 210 may include a large number of wiring layers 212a, 212b, 212c, and 212d, a connection structure 240 may further be simplified. Therefore, a decrease in a yield depending on a defect occurring in a process of forming the connection structure 240 may be suppressed. Meanwhile, the first to fourth wiring layers 212a, 212b, 212c, and 212d may be electrically connected to each other through first to third connection vias 213a, 213b, and 213c respectively penetrating through the first to third insulating layers 211a, 211b, and 211c.
