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Antenna module

專利號
US11177551B2
公開日期
2021-11-16
申請人
SAMSUNG ELECTRONICS CO., LTD.(KR Suwon-si)
發(fā)明人
Won Wook So; Jin Seon Park; Young Sik Hur; Jung Chul Gong; Yong Ho Baek
IPC分類
H01Q1/22; H01Q1/24; H01L23/00; H01L23/66; H01L23/31; H01L23/522
技術(shù)領(lǐng)域
antenna,may,insulating,wiring,layer,package,212a,212b,be,connection
地域: Suwon-si

摘要

An antenna module includes: an antenna substrate including an antenna pattern; a semiconductor package disposed on a lower surface of the antenna substrate, electrically connected to the antenna substrate, and having at least one semiconductor chip embedded therein; and an electronic component disposed on the lower surface or a side surface of the antenna substrate, electrically connected to the antenna substrate, and spaced apart from the semiconductor package by a predetermined distance. The electronic component has a thickness greater than that of the semiconductor chip.

說明書

The wiring layers 212a, 212b, 212c, and 212d may serve to redistribute connection pads 221P and 222P of semiconductor chips 221 and 222. A material of each of the wiring layers 212a, 212b, 212c, and 212d may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The wiring layers 212a, 212b, 212c, and 212d may perform various functions depending on designs of corresponding layers. For example, the wiring layers 212a, 212b, 212c, and 212d may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals except for the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the wiring layers 212a, 212b, 212c, and 212d may include signal via pads, ground via pads, and the like. In addition, the wiring layers 212a, 212b, 212c, and 212d may include feeding patterns.

The first wiring layer 212a and the second wiring layer 212b may be disposed on a level between an active surface and an inactive surface of each of the semiconductor chips 221 and 222. Thicknesses of the wiring layers 212a, 212b, 212c, and 212d of the frame 210 may be greater than those of redistribution layers 242 of the connection structure 240.

權(quán)利要求

1
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