FIG. 1 is a circuit schematic of a typical buck converter with current mode regulation loop. The buck converter comprises an input voltage VIN, an output voltage VOUT, inductor L 40, capacitor C 50, high side switch SH, and low side switch SL. The regulation loop comprises a divider DIV, an operational amplifier OA1 with inputs VOUT/K and VREF, a current sensor RS, a sum function SUM with SLOPE_COMP, a comparator CP1 with positive input RS.IL+SLOPE_COMP and negative input VEA, and flip-flop RS1, which provides output signal MAG to the high side of switch SH. When operating in pulse width modulation (PWM) of constant frequency, a clock CLK periodically issued sets magnetization MAG signal to ‘1’. The inductor current IL through inductor L 40 is sensed and converted to voltage RS.IL, by multiplication of RS. At times, a slope-compensation SLOPE_COMP is added to voltage RS.IL. The comparator CP1 emits signal STOP, and forces magnetization MAG signal to ‘0’, when the total voltage (RS.IL+SLOPE_COMP) exceeds error voltage VEA. VEA sets the target for the maximum inductor current, also called the peak current. Voltage VEA is regulated by the error operational amplifier OA1 to adjust the required peak inductor current to regulate VOUT to a value proportional to VREF. VREF could be generated with a VDAC digital-to-analog converter, using a digital controller. The output voltage of such a buck converter is a voltage supply for other sub-systems.