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Field effect transistor circuits

專利號(hào)
US11177786B1
公開日期
2021-11-16
申請(qǐng)人
Ronald Quan
發(fā)明人
Ronald Quan
IPC分類
H03G3/30; H03G1/00; H03G3/00
技術(shù)領(lǐng)域
fet,q1b,voltage,q1a,drain,rfb,vds,u1a,amplifier,u1b
地域： CA CA Cupertino

摘要

A number of field effect transistor circuits include voltage controlled attenuators or voltage controlled processing circuits. Example circuits include modulators, lower distortion variable voltage controlled resistors, sine wave to triangle wave converters, and or servo controlled biasing circuits.

說明書

This application is a divisional of Ser. No. 16/051,469, which claims priority to U.S. provisional application Ser. No. 62/545,470 filed on Aug. 14, 2017, which is incorporated herein by reference.

BACKGROUND

The present invention relates to Field Effect Transistor (FET) circuits used in providing voltage controlled amplitude circuits, waveform shaping circuits.

SUMMARY

In one embodiment is to provide a lower distortion voltage controlled resistor via an FET, an isolation amplifier or a buffer amplifier was required. For example with a junction FET or JFET, the inclusion of a buffer amplifier did not provide as a substantial difference in lowering distortion when compared to using a MOS (Metal Oxide Silicon) FET or MOSFET. In another example, the inclusion of a buffer amplifier for a depletion mode FET did not provide as a substantial difference in lowering distortion when compared to using an enhancement mode FET. An example such as a DMOS or enhancement mode device such as a SD5000 family of FETs showed much more improvement in reducing or lowering nonlinear distortion (e.g., lowering or reducing harmonic distortion and or lowering or reducing intermodulation distortion) with an amplifier feedback circuit when compared to using feedback network without an amplifier.

One or more embodiments may include the following:

1) An improved voltage controlled resistor including an amplifier.

2) A waveshaping circuit that includes a sinewave to triangle converter circuit.

3) A multiple FET circuit including a feedback circuit to provide a substantially predetermined drain to source resistance or to provide a predetermined amount of attenuation or gain.

權(quán)利要求

1
The invention claimed is:1. A circuit for providing low distortion voltage controlled resistance of an enhancement mode field effect transistor having a drain terminal, a gate terminal, and a source terminal comprising:an amplifier having an input terminal and an output terminal;coupling the drain terminal of the enhancement mode field effect transistor to the input terminal of the amplifier;coupling the output terminal of the amplifier to a first terminal of a first resistor wherein the first resistor includes a second terminal;coupling the second terminal of the first resistor to the gate terminal of the enhancement mode field effect transistor;coupling the gate terminal of the enhancement mode field effect transistor to a first terminal of a second resistor wherein the second resistor includes a second terminal;coupling a first terminal of a control voltage source to the second terminal of the second resistor wherein the control voltage source includes a second terminal;coupling the second terminal of the control voltage source to a ground terminal;coupling the source terminal of the enhancement mode field effect transistor to the ground terminal;providing the low distortion voltage controlled resistance via the drain terminal of the enhancement mode field effect transistor and via the ground terminal and by supplying a predetermined voltage from the control voltage source;wherein the low distortion voltage controlled resistance via the drain terminal of the enhancement mode field effect transistor and the ground terminal provides lower nonlinear distortion compared to when the first terminal of the first resistor is connected to the drain terminal of the enhancement mode field effect transistor instead of the first terminal of the first resistor coupled to the output terminal of the amplifier.2. The circuit of claim 1, wherein the amplifier has a gain of substantially one.3. The circuit of claim 1, wherein the control voltage source is prohibited from being coupled to the drain terminal of the enhancement mode field effect transistor.4. The circuit of claim 2, wherein the first resistor and the second resistor are substantially equal in value.5. The circuit of claim 1, wherein the amplifier has a gain of greater than 1 and that the resistance values for the first and second resistors are chosen to provide half the voltage at the drain terminal of the enhancement mode field effect transistor to the gate terminal of the enhancement mode field effect transistor.6. The circuit of claim 1, that further includes a third resistor with a first terminal and a second terminal, further comprising:an input signal voltage source coupled to the first terminal of the third resistor;the second terminal of the third resistor is coupled to the drain terminal of the enhancement mode field effect transistor;providing an output terminal coupled to the drain of the enhancement mode field transistor;wherein the output terminal provides a symmetrical clipping characteristic that includes voltage controlled clipping levels via adjusting the control voltage source.
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