In FIG. 7B, amplifier U1A has a gain, G=[(R10+R11)/(R11)=1+(R10/R11). The drain voltage is amplified by a factor of G at Vout_A. To provide for a linearized drain to source voltage control resistance, 50% of the drain voltage of Q3 should be coupled to the gate of Q3. The resistor values of Rib and R7 are chosen such that: G[(R7)/(R7+Rfb)]=?. Or in other words, [(R7+Rfb)/(R7)]=2G, which equivalently states that (Rfb/R7)=2G?1. For example if G=10 (e.g., R10/R11=9, such as R10=18 kΩ and R11=2 kΩ, then (Rfb/R7)=2×10?1=20?1=19 or (Rfb/R7)=19, which can have example values of: Rfb=1900 kΩ (1.9 MΩ) and R7=100 kΩ. One other advantage to having R7<<Rfb due to G>1 is that the control voltage is almost completely coupled to the gate terminal of the FET Q3 (e.g., 1?1/(2G); for example if G=10, the transferred voltage is 1?1/(2G)=1?1/(2×10)=1?0.05=95% transferred to the gate of the FET, Q3.
In the FIGS. 3, 4, 5, 6, and 7A, the control voltage from the wiper or slider of VR1 is transferred to the gate at half or 50%. This results in that to provide a full range of attenuation, twice the voltage is required at the wiper of VR1. FIG. 7B with G>1 allows for less than twice the voltage at the wiper of VR1 to provide a full range of attenuation from the voltage controlled resistor FET.
