FIG. 14 shows another embodiment where a linearized voltage controlled resistor (e.g., via feedback network Rfb and R4) is included to provide a voltage controlled gyrator (e.g., simulated inductor) circuit via the drain to source resistance of FET Q1A, C1, U1A, and Rs. The gyrator equivalently provides an inductor in parallel to C_res. The gyrator's inductance L=RsC1RdsQ1A with a series resistance of Rs. RdsQ1A is the drain to source resistance of FET Q1A that is controlled by ?Vbias and or Vww. The gyrator can be modeled as an ideal inductor of L in series with a resistor Rs (e.g., L+Rs). With C_res in parallel with the gyrator, a parallel inductor-capacitor band pass filter circuit is provided. This parallel inductor-capacitor band pass circuit may be coupled to a current source or may be coupled to a driving resistor, VR1 as shown in FIG. 14. The quality factor of the bandpass filter circuit is:
Q?2πfres (VR1)(C_res), where Rs is sufficiently small in resistance to provide an unloaded Qu>Q.
In FIG. 14 the FET Q1A may be replaced with an enhancement mode (e.g., N-channel) FET providing that ?Vbias→+Vbias. The output amplifier U1B provides the band pass filtered signal to a load without affecting the Q of the parallel capacitor gyrator (e.g., gyrator is a simulated inductor) bandpass filter circuit. Amplifier U1A provides isolation from the Vww or the DC bias voltage, ?Vbias for depletion mode N channel FET (e.g., for Q1A) or having +Vbias for enhancement mode N Channel FET (e.g., for Q1A). Amplifier U1A also provides improved distortion reduction when enhancement mode FETs are included (e.g., as Q1A).
