Alternatively in FIG. 15, the resistor R3 may be smaller in resistance value such that the control voltage (e.g., at the slider or wiper of VR1) is amplified with a gain >1 via U1B and U3A (e.g., gain=R4/R3) and transferred or coupled to the gate of the FET (e.g., Q2B). This greater than 1 gain of the control voltage allows for a smaller voltage for the control voltage (e.g., at the wiper or slider of VR1) when compared to the circuits in FIG. 1, 2, 3, 4, 5, and or 6. FIG. 15 includes a JFET or depletion mode device (e.g., Q2B). FIG. 16 shows essentially the same circuit as FIG. 15 that includes an enhancement mode FET or MOSFET (e.g., U2A) instead of a depletion mode FET or JFET.

FIG. 17 shows an embodiment for reducing at least one even order harmonic or intermodulation distortion via driving two FET voltage controlled resistors in balanced or push pull mode. The signals from the drain terminals of the two FET voltage controlled resistors are subtracted via a differential amplifier (e.g. U2B) that cancels or reduces even order harmonic distortion, and or that cancels or reduces even order intermodulation distortion. A push pull or balanced signal is provided by an in-phase signal coupled to a first FET Q1A and an out of phase signal (e.g., inverted phase signal) provided by inverting amplifier circuit R12, R11, and U1B. The out of phase signal from U1B is coupled to a second FET Q1B. Vbias supplies a negative bias voltage to control the drain to source resistances of FETs Q1A and Q1B. Preferably Q1A and Q1B are matched.