In FIG. 20 a modulated drain to source resistance may be provided by coupling a signal to the gate of Q1A via signal source Vww and C3, and or coupling or combining a signal on either side of R8 (note that R8 is shown to have 10 KΩ of resistance, but other resistance values may be used), or combining or coupling a modulating signal to the wiper of VR2, or coupling a modulating to the (?) input terminal of U3A. Diode D1 in FIG. 20 has its anode coupled to the gate of Q1B and to the input terminal of A102. To ensure proper start-up of the bias servo circuit in FIG. 20, D1 ensures that the gate terminals of Q1B and Q1A avoid being forward biased, which may cause U3A to latch to a positive voltage, which would be incorrect since the N channel (e.g., depletion mode) devices of Q1B and Q1A require a non positive voltage their gate terminals or generally a negative bias voltage at their gate terminals. Diode D1 may include a germanium diode or a Schottky diode, which either or both provide forward diode drop voltages less than the forward bias drop voltage across the gate and source of the FETs Q1B and Q1A. The gate terminals of Q1A and Q1B are biased with substantially the same DC voltage to ensure substantially equal quiescent drain to source resistance for Q1B and Q1A. Modulation of the drain to source resistance of Q1A is provided by AC coupling voltage signal Vww via C3 to the gate of Q1A. DC biasing to Q1A is provided by R1 via the output of A102. The output voltage or signal from A102 is substantially the same as the gate terminal voltage of Q1B.