(
                
                  1
                  Vp
                
                )
              
              ?
              
                (
                
                  1
                  -
                  
                    Vgs
                    Vp
                  
                
                )
              
            
            -
            
              2
              ?
              
                (
                
                  Vds
                  Vp
                
                )
              
              ?
              
                (
                
                  1
                  Vp
                
                )
              
            
          
          ]
        
      
      }
    
  
FIG. 2 shows an enhancement mode FET (e.g., Q2) voltage controlled resistor prior art circuit. In this circuit at 0 volts across the gate and source, the drain to source resistance is nearly infinite and the output signal Vout is almost equal to Vin. If the gate to source voltage of Q2 is increased to a positive voltage sufficiently high to provide a very low resistance from its drain to source terminal, only a small fraction of Vin will pass to Vout.
For an enhancement device, drain current, Id, can be characterized by the following equation in the FET's ohmic or triode region that is generally used for resistance across the drain and source terminals: