What is claimed is:1. A glitch absorbing buffer, comprising:a logic element comprising an inverter and an AND gate, configured to identify a digital logic glitch; anda delay circuit in communication with the logic element, in which the delay circuit is configured to input a signal to a first input of the AND gate and input an inverted, delayed version of the signal to a second input of the AND gate, and to output a pulse having a width equal to the digital logic glitch.2. The glitch absorbing buffer of claim 1, in which the logic element configured to identify the digital logic glitch is a C-element.3. The glitch absorbing buffer of claim 2, in which the C-element is configured to determine an overlap between the first input and a second input to the logic element.4. The glitch absorbing buffer of claim 3, in which the C-element is configured to toggle an output signal when a filtered pulse width is wider than or equal to an amount of delay (δBUF).5. The glitch absorbing buffer of claim 3, in which the C-element is configured not to toggle an output signal when a filtered pulse width is less than an amount of delay (δBUF).6. The glitch absorbing buffer of claim 1, further comprising an internal buffer delay configured to determine a filtered pulse width.7. The glitch absorbing buffer of claim 1, in which the logic element configured to identify a digital logic glitch incorporates a Schmitt trigger.8. The glitch absorbing buffer of claim 7, in which the Schmitt trigger is configured to compare a pulse width with the glitch.9. The glitch absorbing buffer of claim 8, in which the Schmitt trigger is configured to toggle when the pulse width is equal to or greater than an amount of delay (δBUF).10. A method of reducing glitch power in digital logic, comprising:determining whether two inputs arrive separately at a logic element, the two inputs comprising an original input and a delayed version of the original input;determining an amount of delay between an arrival of the two inputs at the logic element when the two inputs arrive separately;defining a pulse width as an amount of delay (δBUF) between the arrival of the two inputs;determining whether there is an overlap in the arrival between the two inputs; andtoggling the logic element when the two inputs overlap in the arrival, in which the toggling inputs an inverted and delayed version of the original input to the logic element.11. The method of claim 10, further comprising comparing a pulse width with the glitch and toggling the logic element when the pulse width is equal to or greater than the amount of delay (δBUF).12. The method of claim 11, in which the logic element toggles only when the two inputs agree in value, both high or both low.13. The method of claim 12, further comprising keeping a previous state when the two inputs do not agree in value.14. The method of claim 10 further comprising:operating a glitch absorbing buffer in a delay mode where there is the overlap in arrival on transitional states; andoperating the glitch absorbing buffer in a filter mode on narrow glitches that do not overlap on transitional states.15. A glitch absorbing buffer, comprising:means for identifying a digital logic glitch; andmeans for selectively inverting and delaying one input to the means for identifying.16. The glitch absorbing buffer of claim 15, further comprising means for determining an overlap between the one input and a second input.17. The glitch absorbing buffer of claim 15, further comprising means for determining a filtered pulse width.18. The glitch absorbing buffer of claim 15, in which the means for identifying a digital logic glitch incorporates a Schmitt trigger.19. The glitch absorbing buffer of claim 18, further comprising means for comparing a pulse width with the digital logic glitch.20. The glitch absorbing buffer of claim 19, further comprising means for toggling when the pulse width is equal to or greater than an amount of delay.
