The C-element based glitch absorbing buffer (GABUF), which may also be known as a glitch suppressor circuit, described is combined with complex scripts that analyze the logic cone design and identify a number of points at which this glitch suppressor cell may be added to reduce the overall glitch power of the design without affecting functionality. This may specify a complex framework of timing analysis so that the cell may be inserted and other logic cones balanced so that the C-element cell does not create additional glitches downstream. The method and apparatus described may reduce dynamic power consumption in chips.

Aspects of the present disclosure are directed to improving power management and low power design by providing a glitch absorbing buffer (GABUF) having a delay element. The GABUF may be selectively added to a design, such as on a data path where the logic may be prone to glitches.

A glitch is an unwanted switching in a digital logic circuit due to routing resource timing delay variances. Glitches occur on combinational logic because the logic elements react asynchronously to their input signals. Downstream logic may be susceptible to glitches, on both synchronous and asynchronous signal paths. This delay may occur due to differences in the signal routing paths or layout. This behavior results in additional switching, which increases power consumption. Power is wasted because each pulse demands a rise and fall event, which may also result in additional power wasted downstream from the glitch. Glitches may also inject more noise into a design through coupling on signal paths. In addition, glitches may compound as signals traverse the logic hierarchy and may affect the power of the receiving flops where the master latch is transparent to the glitches.