FIG. 6A is a block diagram illustrating a cell concept of a glitch absorbing buffer (GABUF) 600, according to aspects of the present disclosure. The GABUF 600 is a single input logic gate. Internally, the GABUF 600 splits the input signal into two versions, one of which is delayed. The amount of the delay between the two inputs defines the glitch time threshold, e.g., a pulse smaller than this delay is classified as a glitch. Pulses larger than the glitch time threshold are classified as valid signal pulses. The GABUF 600 buffers an input signal a and filters any glitches, preventing the glitches from appearing at an output z. A signal waveform in FIG. 6B shows the original input a and the output z. The GABUF 600 adjusts the timing by delaying one input to the logic element. The GABUF 600 identifies glitches based on timing differences and the result is that the filtered glitch bandwidths are hardcoded into the logic cell. FIG. 6B is a timing diagram showing a glitch on a signal waveform, according to aspects of the present disclosure. The timing delay is noted as δglitch in the signal waveform diagram of FIG. 6B. During the design process, the GABUFs 600 may be added based on the path lengths that produce glitches. As illustrated in FIG. 6B, the original input signal a with a δglitch is filtered by the GABUF 600 to produce the clean output signal waveform z.
