FIG. 9A is a cell schematic of a GABUF 900, according to aspects of the present disclosure. The GABUF 900 assembly includes the C-element 800 of FIG. 8A and a pulse delay (δBUF) 902, which represents the delay in the signal path. The inputs to the C-element 800 are input signals a and a delayed input signal ad. The C-element 800 then produces an output signal z. FIG. 9B is a timing diagram showing the effect of toggling the logic element (e.g., C-element 800) in the GABUF 900, according to aspects of the present disclosure. The signaling waveforms in FIG. 9B show the relationship between an input signal a, which is not delayed, and an input signal ad, which is a delayed version of signal a. If the input pulse width is smaller than the pulse delay δBUF 902, then there is no overlap between signal a and signal ad, and the C-element 800 does not toggle. If the input pulse width is larger than the pulse delay δBUF 902, then the C-element 800 will toggle, as shown in the signal waveforms in FIG. 9B. Therefore, the pulse delay δBUF 902 defines the threshold between a glitch and a non-glitch pulse.
