FIG. 10A is a block diagram showing a further cell schematic of a glitch absorbing buffer (GABUF), according to aspects of the present disclosure. A GABUF assembly 1000 includes an input signal a with an upper branch having a pulse delay δ_BUF 902. The input signal a may be routed to a complementary metal oxide semiconductor (CMOS) transistor 1002b, while a second input signal is affected by the pulse delay δ_BUF 902 and arrives at a CMOS transistor 1002a after a delay period. The CMOS transistor 1002a provides input to CMOS transistors 1004 and 1006b. A CMOS transistor 1002b provides input to CMOS transistors 1004 and 1006a. The CMOS transistor 1004 outputs to a logic inverter 1008a. The logic inverter 1008a is in communication with logic inverters 1008b and 1008c. The logic inverter 1008b provides an output signal z_b. The design is mirrored with a logic inverter 1008c connected to a logic inverter 1014. A CMOS transistor 1010a is connected to the pulse delay δ_BUF 902 as are CMOS transistors 1006a and 1016a. A CMOS transistor 1010b is similarly connected to the input signal along with the CMOS transistor 1006b. The CMOS transistor 1010a is connected to the CMOS transistor 1016b and the CMOS transistor 1010b is connected to the CMOS transistor 1016a. The GABUF assembly 1000 identifies if there is an overlap in signal timing.