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Reducing glitch power in digital circuits

專利號(hào)
US11177805B1
公開日期
2021-11-16
申請(qǐng)人
QUALCOMM Incorporated(US CA San Diego)
發(fā)明人
Harshat Pant; Ravindraraj Ramaraju; Luis Filipe Brochado Reis; Tuck Boon Chan; Mayank Sen Sharma
IPC分類
H03K5/00; H03K19/003
技術(shù)領(lǐng)域
glitch,glitches,logic,signal,delay,in,input,absorbing,disclosure,may
地域: CA CA San Diego

摘要

A glitch absorbing buffer reduces glitch power in digital circuits. The glitch absorbing buffer includes a logic element configured to identify a digital logic glitch and a delay circuit configured to selectively delay one input to a logic element. The amount of delay imposed is equivalent to a pulse width of the glitch. A Schmitt trigger may amplify the low pass behavior on the input.

說明書

If implemented in firmware and/or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media includes physical computer storage media. A storage medium may be an available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer; disk and disc, as used, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

In addition to storage on computer-readable medium, instructions and/or data may be provided as signals on transmission media included in a communications apparatus. For example, a communications apparatus may include a transceiver having signals indicative of instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

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