A chipset according to this disclosure is included in a first communication apparatus that performs relay transmission between a network and a second communication apparatus. The chipset comprises a processor and a memory coupled to the processor. The processor is configured to perform processes of receiving a system information block (SIB) broadcasted from a base station, and while the user equipment is in a radio resource control (RRC) idle mode in which no RRC connection is established between the use equipment and the base station, the SIB used to control the D2D communication. The processor is configured to transmit data to other user equipment by the D2D communication based on the SIB while the user equipment is in the RRC idle mode. The SIB includes resource information indicating usable radio resources for the D2D communication and power information used for controlling transmission power in the D2D communication. In the process of the transmitting, the processor configured to perform processes of determining radio resources used to transmit the data based on the resource information, determining transmission power used in transmitting the data based on the power information, and transmitting the data using the determined radio resources and the determined transmission power.