In the described embodiment, a highly complex high-performance vertical electric connection circuitry within the electronic device 100 is achieved by the vertically tilted second electrically conductive layer structures 110 of the second component carriers 108.

In the following, a method of manufacturing the electronic device 100 shown in FIG. 10 will be described referring to FIG. 1 to FIG. 9. This embodiment relates to a chip first architecture.

Referring to FIG. 1, a cross-sectional view of a PCB-type first component carrier 102 is shown which comprises first electrically conductive layer structures 104 (preferably made of copper) on both opposing main surfaces and extending vertically through a first electrically insulating layer structure 106 (which may comprise epoxy resin with reinforcing glass fibers). A cavity 114 is formed as a through hole extending through the electrically insulating layer structure 106. A bottom of the cavity 114 is closed by a temporary carrier 170, such as a sticky tape, attached to a lower main surface of the arrangement composed of the first electrically insulating layer structure 106 and the electrically conductive layer structures 104. Thus, FIG. 1 shows the temporary carrier 170 below a board as first component carrier 102 having the cavity 114.