Reduced rendering of six-degree of freedom video
摘要
說明書
In one embodiment the SoC interface 537 enables the graphics core 500 to communicate with general-purpose application processor cores (e.g., CPUs) and/or other components within an SoC, including memory hierarchy elements such as a shared last level cache memory, the system RAM, and/or embedded on-chip or on-package DRAM. The SoC interface 537 can also enable communication with fixed function devices within the SoC, such as camera imaging pipelines, and enables the use of and/or implements global memory atomics that may be shared between the graphics core 500 and CPUs within the SoC. The SoC interface 537 can also implement power management controls for the graphics core 500 and enable an interface between a clock domain of the graphic core 500 and other clock domains within the SoC. In one embodiment the SoC interface 537 enables receipt of command buffers from a command streamer and global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. The commands and instructions can be dispatched to the media pipeline 539, when media operations are to be performed, or a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline 536, geometry and fixed function pipeline 514) when graphics processing operations are to be performed.
