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Reduced rendering of six-degree of freedom video

專利號(hào)
US11212506B2
公開(kāi)日期
2021-12-28
申請(qǐng)人
Intel Corporation（US CA Santa Clara）
發(fā)明人
Jill Boyce
IPC分類
H04N13/178; H04N13/398; H04N13/366
技術(shù)領(lǐng)域
graphics,pipeline,shader,in,video,processor,data,or,execution,texture
地域： CA CA Santa Clara

摘要

Embodiments described herein provide for techniques to reduce the complexity of rendering immersive 3D video content. One embodiment provides for an apparatus comprising one or more processors to receive a data set that represents a two-dimensional encoding of planar projections of a frame of a three-dimensional video, decode the two-dimensional encoding into texture data, geometry data, and metadata, determine, based on the metadata, a visibility status and an occupancy status for a sample position in the three-dimensional video, and render video data for the sample position when the sample position is visible and occupied.

說(shuō)明書(shū)

The graphics core 500 may have greater than or fewer than the illustrated sub-cores 501A-501F, up to N modular sub-cores. For each set of N sub-cores, the graphics core 500 can also include shared function logic 510, shared and/or cache memory 512, a geometry/fixed function pipeline 514, as well as additional fixed function logic 516 to accelerate various graphics and compute processing operations. The shared function logic 510 can include logic units associated with the shared function logic 420 of FIG. 4 (e.g., sampler, math, and/or inter-thread communication logic) that can be shared by each N sub-cores within the graphics core 500. The shared and/or cache memory 512 can be a last-level cache for the set of N sub-cores 501A-501F within the graphics core 500 and can also serve as shared memory that is accessible by multiple sub-cores. The geometry/fixed function pipeline 514 can be included instead of the geometry/fixed function pipeline 536 within the fixed function block 530 and can include the same or similar logic units.

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