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Reduced rendering of six-degree of freedom video

專利號
US11212506B2
公開日期
2021-12-28
申請人
Intel Corporation(US CA Santa Clara)
發(fā)明人
Jill Boyce
IPC分類
H04N13/178; H04N13/398; H04N13/366
技術(shù)領(lǐng)域
graphics,pipeline,shader,in,video,processor,data,or,execution,texture
地域: CA CA Santa Clara

摘要

Embodiments described herein provide for techniques to reduce the complexity of rendering immersive 3D video content. One embodiment provides for an apparatus comprising one or more processors to receive a data set that represents a two-dimensional encoding of planar projections of a frame of a three-dimensional video, decode the two-dimensional encoding into texture data, geometry data, and metadata, determine, based on the metadata, a visibility status and an occupancy status for a sample position in the three-dimensional video, and render video data for the sample position when the sample position is visible and occupied.

說明書

In the following description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. “Coupled” is used to indicate that two or more elements, which may or may not be in direct physical or electrical contact with each other, co-operate or interact with each other. “Connected” is used to indicate the establishment of communication between two or more elements that are coupled with each other.

In the description that follows, FIGS. 1-14 provide an overview of exemplary data processing system and graphics processor logic that incorporates or relates to the various embodiments. FIGS. 15-24 provide specific details of the various embodiments. Some aspects of the following embodiments are described with reference to a graphics processor, while other aspects are described with respect to a general-purpose processor, such as a central processing unit (CPU). Similar techniques and teachings can be applied to other types of circuits or semiconductor devices, including but not limited to a many integrated core processor, a GPU cluster, or one or more instances of a field programmable gate array (FPGA). In general, the teachings are applicable to any processor or machine that manipulates or processes image (e.g., sample, pixel), vertex data, or geometry data.

System Overview

權(quán)利要求

1
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