FIG. 23 is a diagram for explaining an example of approximation of a phase fluctuation.
FIG. 24 is a diagram illustrating a result of decoding.
FIG. 25 is a diagram illustrating examples of primary functions of an interference suppression processing unit with an equivalent circuit.
FIG. 26 is a flowchart for explaining an example flow of an interference suppression process.
FIG. 27 is a flowchart for explaining an example flow of an approximate replica generation process.
FIG. 28 is a diagram illustrating examples of primary functions of an interference suppression processing unit with an equivalent circuit.
FIG. 29 is a flowchart for explaining an example flow of an approximate replica generation process.
FIG. 30 is a diagram illustrating examples of primary functions of an interference suppression processing unit with an equivalent circuit.
FIG. 31 is a flowchart for explaining an example flow of an approximate replica generation process.
FIG. 32 is a block diagram illustrating a configuration example of primary parts of a computer.
DESCRIPTION OF EMBODIMENTS
Hereinafter, modes for carrying out the present disclosure (hereinafter referred to as embodiments) will be described. Descriptions will be provided in the following order.
