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Apparatus with a substrate provided with plasma treatment

專利號(hào)
US11291122B2
公開日期
2022-03-29
申請(qǐng)人
Intel Corporation（US CA Santa Clara）
發(fā)明人
Darko Grujicic; Rengarajan Shanmugam; Sandeep Gaan; Adrian Bayraktaroglu; Roy Dittler; Ke Liu; Suddhasattwa Nad; Marcel A. Wall; Rahul N. Manepalli; Ravindra V. Tanikella
IPC分類
C23C18/38; H05K3/38; C23C18/16; C23C18/18; H01L21/48; H05K3/42; H05K3/46; H05K1/11; H01L23/14
技術(shù)領(lǐng)域
may,substrate,in,plating,metal,copper,surface,die,or,catalyst
地域： CA CA Santa Clara

摘要

Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.

說明書

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a national phase entry under 35 U.S.C. § 371 of International Application No. PCT/US2017/053068, filed Sep. 22, 2017, entitled “AN APPARATUS WITH A SUBSTRATE PROVIDED WITH PLASMA TREATMENT”, which designated, among the various States, the United States of America. The disclosure of International Application No. PCT/US2017/053068 is hereby incorporated by reference in its entirety.

FIELD

Embodiments of the present disclosure generally relate to the field of semiconductor package and printed circuit board (PCB) fabrication and in particular to techniques for improving surfaces of substrates used in semiconductor packages or PCB.

BACKGROUND

Electroless deposition is routinely employed in electronic industry to form a seed layer in substrates that could be utilized to form metallic interconnects on buildup films/composite polymeric materials. Buildup films in semiconductor packaging typically include epoxy resins, surface finish films, molding compounds, photo imageable dielectrics, and other types of organic films. Achieving uniform surface coverage for various substrate materials is crucial and may be particularly challenging with polymeric composite materials that do not provide sufficiently active surface sites that favor electroless plating reactions through the complex physicochemical interactions.

權(quán)利要求

1
What is claimed is:1. An apparatus, comprising:a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus, wherein the metal layer is provided in response to a treatment of the surface with a gas containing a functional group, to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal, wherein the transition metal catalyst is to enhance electroless plating of the surface with the metal, wherein, prior to the electroless plating, the transition metal catalyst comprises a plurality of seed protrusions disposed on the surface, wherein the metal layer comprises metal growth including a plurality of metal bumps deposited on the surface on top of the plurality of seeds such that the metal growth covers the plurality of seeds.2. The apparatus of claim 1, wherein the substrate comprises a dielectric material, wherein the material includes one of: epoxy resin, surface finish film, molding compound, solder resist, or photo imageable dielectric.3. The apparatus of claim 1, wherein the metal layer includes copper, wherein the treatment comprises a plasma treatment.4. The apparatus of claim 1, wherein the functional group comprises a nitrogen gas or a gas that contains nitrogen.5. The apparatus of claim 1, wherein the transition metal catalyst comprises an ionic or colloidal palladium.6. The apparatus of claim 1, further comprising a die disposed on the substrate.7. The apparatus of claim 6, wherein the apparatus further includes one or more vias arranged in the substrate, to provide the signal routing for signals generated by the die.8. The apparatus of claim 1, wherein the apparatus comprises a semiconductor package.9. The apparatus of claim 1, wherein the apparatus comprises a printed circuit board (PCB).10. A computing device, comprising: a processor; and a memory coupled with the processor; wherein at least one of the processor or memory comprises an integrated circuit (IC), wherein the IC includes: a substrate with a surface that comprises a layer that contains a metal to provide signal routing for the IC, wherein the metal layer is provided in response to a plasma treatment of the surface with a gas containing a functional group, to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal, wherein the transition metal catalyst is to enhance electroless plating of the surface with the metal, wherein, prior to the electroless plating, the transition metal catalyst comprises a plurality of seed protrusions disposed on the surface, wherein the metal layer comprises metal growth including a plurality of metal bumps deposited on the surface on top of the plurality of seeds such that the metal growth covers the plurality of seeds.11. The computing device of claim 10, wherein the functional group comprises a nitrogen gas or a gas that contains nitrogen.12. The computing device of claim 10, wherein the transition metal catalyst comprises a palladium.13. The computing device of claim 10, wherein the substrate includes one or more vias arranged in the substrate, to provide the signal routing for signals generated by the processor.14. The computing device of claim 10, wherein the at least one of the processor or memory is provided in a die, wherein the die is disposed on the substrate.
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