The one or more top O-layers 332 may include a top U-layer 340a, a top V-layer 340b, and a top W-layer 340c. Similarly, the one or more bottom O-layers 334 include a bottom U-layer 342a, a bottom V-layer 342b, and a bottom W-layer 342c. Additionally, each of the plurality of intermediate O-layers includes an intermediate U-layer 344a, an intermediate V-layer 344b, and an intermediate W-layer 344c. Each of the intermediate U-layer 344a, intermediate V-layer 344b, and intermediate W-layer 344c may include any number of layers (e.g., one or more layers, two or more layers, three or more layers, four or more layers, and the like). When laminated together in the PCB substrate 110, each of the U-layers may be electrically and thermally coupled to one another, each of the V-layers may be electrically and thermally coupled to one another, and each of the W-layers may be electrically and thermally coupled to one another. For example, each layer of the O-conductive layer architecture 316 (i.e., each layer of the U-conductive layer architecture 338a, each layer of the V-conductive layer architecture 338b, and each layer of the W-conductive layer architecture 338c) may by in contact with one another (e.g., either directly contacted with one another or in contact through the plurality of vias 206 such as those illustrated in