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Channel measurement techniques in discontinuous reception scenarios

專利號
US11503489B2
公開日期
2022-11-15
申請人
QUALCOMM Incorporated(US CA San Diego)
發(fā)明人
Pranay Sudeep Rungta; Shailesh Maheshwari; Sanjana Vijaykumar Kalyanappagol; Ankit Verma
IPC分類
H04W76/28; H04W24/10; H04B17/318; H04B7/06; H04W72/04; H04L5/00; H04B17/336
技術領域
ue,drx,channel,csi,may,in,be,reception,or,mode
地域: CA CA San Diego

摘要

Methods, systems, and devices for wireless communications are described for configuring a user equipment (UE) for reference signal measurement while operating according to a discontinuous reception (DRX) configuration. The DRX configuration may include periodic DRX ON-durations, during which the UE is to be in an active mode for reception and transmission of signals, and between which the UE may transition to a low-power inactive mode. One or more reference signals may be scheduled for transmission by the base station during periods in which the UE may be in the inactive mode, and the UE may skip monitoring one or more of the reference signals while in the inactive mode. For one or more reference signal occasions, the UE may determine, based at least in part on a change in a channel quality metric, to be in a limited active mode in order to measure the reference signal.

說明書

The memory 1030 may include RAM and ROM. The memory 1030 may store computer-readable, computer-executable code 1035 including instructions that, when executed, cause the processor to perform various functions described herein. In some cases, the memory 1030 may contain, among other things, a BIOS which may control basic hardware or software operation such as the interaction with peripheral components or devices.

The processor 1040 may include an intelligent hardware device, (e.g., a general-purpose processor, a DSP, a CPU, a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof). In some cases, the processor 1040 may be configured to operate a memory array using a memory controller. In other cases, a memory controller may be integrated into the processor 1040. The processor 1040 may be configured to execute computer-readable instructions stored in a memory (e.g., the memory 1030) to cause the device 1005 to perform various functions (e.g., functions or tasks supporting channel measurement techniques in discontinuous reception scenarios).

The code 1035 may include instructions to implement aspects of the present disclosure, including instructions to support wireless communications. The code 1035 may be stored in a non-transitory computer-readable medium such as system memory or other type of memory. In some cases, the code 1035 may not be directly executable by the processor 1040 but may cause a computer (e.g., when compiled and executed) to perform functions described herein.

權利要求

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