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Determination of application delay value of minimum scheduling offset limit

專利號(hào)
US11516831B2
公開日期
2022-11-29
申請(qǐng)人
LG Electronics Inc.(KR Seoul)
發(fā)明人
Inkwon Seo; Joonkui Ahn
IPC分類
H04W72/12; H04L27/26; H04W72/04
技術(shù)領(lǐng)域
k0,scheduling,ue,dci,slot,k2,may,pdcch,cell,in
地域: Seoul

摘要

Provided are a method and device for determining an application delay value of a minimum scheduling offset limit in a wireless communication system. In the method, when DCI including information notifying a change in a minimum scheduling offset limit value in slot n of a scheduling cell is received, the changed minimum scheduling offset limit value is applied in slot n+X of the scheduling cell. Here, the X value may be determined on the basis of two parameters such as Y and Z, wherein the Y value is a minimum scheduling offset limit value applied to a scheduled cell scheduled by the DCI, and the Z value is a value determined in advance according to a subcarrier interval of the scheduling cell. In addition, the Z value may be increased by 1 according to the temporal position at which the DCI is received in the slot n.

說明書

3 2 Type A 0 2 9 3 Type A 0 3 8 4 2 Type A 0 2 7 3 Type A 0 3 6 5 2 Type A 0 2 5 3 Type A 0 3 4 6 2 Type B 0 9 4 3 Type B 0 10 4 7 2 Type B 0 4 4 3 Type B 0 6 4 8 2, 3 Type B 0 5 7 9 2, 3 Type B 0 5 2 10 2, 3 Type B 0 9 2 11 2, 3 Type B 0 12 2 12 2, 3 Type A 0 1 13 13 2, 3 Type A

權(quán)利要求

1
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