Referring to FIG. 26, the processor 3000 may include a control information/data generation module 3010 and a transmission module 3020. The processor 3000 may execute the methods described from the perspective of the transmitter in FIGS. 16 to 20. For example, the processor 3000 transmits, to a user equipment, downlink control information (DCI) including information for a change to a value of K0 min or K2 min in a slot n of a scheduling cell, each of the K0 min and K2 min being an applied minimum scheduling offset restriction. The processor 3000 may assume that the changed K0 min or the changed K2 min value is applied in the slot n+X of the scheduling cell. The X value is a largest value among i) a first value obtained by multiplying currently applied K0 min (Y) in a scheduled cell scheduled by the DCI by 2μscheduling/2μscheduled and then performing ceiling and ii) a second value (Z) that are predetermined depending on a subcarrier spacing (SCS) of the scheduling cell. The μscheduling is a subcarrier spacing configuration of the scheduling cell and the μscheduled is a subcarrier spacing configuration of the scheduled cell. The processor 3000 may be an example of the processors 102 and 202 of FIG. 21.
FIG. 27 shows another example of a wireless device.
According to FIG. 27, a wireless device may include at least one processor 102, 202, at least one memory 104, 204, at least one transceiver 106, 206, and one or more antennas 108, 208.
