FIG. 7 illustrates sequence numbers 01 to 08 for signals to be processed with respect to a plurality of pixel circuits 10. First, the first pixel set 16 is selected by a scanning circuit, not illustrated. For example, signals of pixel circuits 10 of the (ρ×λ+1)-th row, signals of pixel circuits 10 of the (ρ×λ+2)-th row, signals of pixel circuits 10 of the (ρ×λ+3)-th row, signals of pixel circuits 10 of the (ρ×λ+4)-th row are sequentially processed (sequence numbers 01 to 04). Next, the next pixel set 16 is selected by the scanning circuit, not illustrated. In other words, signals of pixel circuits 10 of ((ρ+1)×λ+1)-th row, signals of pixel circuits 10 of ((ρ+1)×λ+2)-th row, signals of pixel circuits 10 of ((ρ+1)×λ+3)-th row, signals of pixel circuits 10 of ((ρ+1)×λ+4)-th row are read out to the signal lines 14. Then, the input unit 210 and the main unit 220 sequentially process (sequence numbers 05 to 08) signals of pixel circuits 10 of ((ρ+1)×λ+2)-th row, signals of pixel circuits 10 of ((ρ+1)×λ+3)-th row, signals of pixel circuits 10 of ((ρ+1)×λ+4)-th row.
