Alternatively, the CORESET bandwidth is implicitly indicated by a number of symbols occupied by the control resource set in a slot; for example, the number of symbols occupied by the CORESET in a slot is 1, which corresponds to that the CORESET bandwidth is 48 PRBs; and when the number of symbols occupied by the CORESET in the slot is 2, and the CORESET bandwidth is 24 PRBs. In this case, it is unnecessary to introduce a bandwidth indication bit separately.
Implementation Manner 2:
The present implementation manner describes an indication of CORESET frequency domain position information, which is described as follows: the configuration information of the control resource set includes the frequency domain position information of the control resource set; where the frequency domain position is indicated by a frequency offset between the control resource set and a synchronization signal block.